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Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/633
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dc.contributor.authorTurner, Kenneth Jen_UK
dc.contributor.authorHe, Jien_UK
dc.contributor.editorMargaria, Tizianaen_UK
dc.contributor.editorMelham, Thomas Fen_UK
dc.date.accessioned2017-08-21T23:04:20Z-
dc.date.available2017-08-21T23:04:20Z-
dc.date.issued2001en_UK
dc.identifier.urihttp://hdl.handle.net/1893/633-
dc.description.abstractThis paper investigates specification, verification and test generation for synchronous and asynchronous circuits. The approach is called DILL (Digital Logic in LOTOS). DILL models are discussed for synchronous and asynchronous circuits. Relations for (strong) conformance are defined for verifying a design specification against a high-level specification. An algorithm is also outlined for generating and applying implementation tests based on a specification. Tools have been developed for automated test generation and verification of conformance between an implementation and its specification. The approach is illustrated with various benchmark circuits as case studies.en_UK
dc.language.isoenen_UK
dc.publisherSpringer Verlagen_UK
dc.relationTurner KJ & He J (2001) Formally-Based Design Evaluation (extended version). In: Margaria T & Melham TF (eds.) Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science, volume 2144. CHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Livingston, Scotland, 04.09.2001-07.09.2001. Berlin: Springer Verlag, pp. 104-109. https://doi.org/10.1007/3-540-44798-9en_UK
dc.relation.ispartofseriesLecture Notes in Computer Science, volume 2144en_UK
dc.rightsPublished by Springer Verlag. The original publication is available at www.springerlink.comen_UK
dc.titleFormally-Based Design Evaluation (extended version)en_UK
dc.typeConference Paperen_UK
dc.identifier.doi10.1007/3-540-44798-9en_UK
dc.citation.spage104en_UK
dc.citation.epage109en_UK
dc.citation.publicationstatusPublisheden_UK
dc.citation.peerreviewedRefereeden_UK
dc.type.statusAM - Accepted Manuscripten_UK
dc.author.emailkjt@cs.stir.ac.uken_UK
dc.citation.btitleCorrect Hardware Design and Verification Methodsen_UK
dc.citation.conferencedates2001-09-04 - 2001-09-07en_UK
dc.citation.conferencelocationLivingston, Scotlanden_UK
dc.citation.conferencenameCHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methodsen_UK
dc.citation.isbn978-3-540-42541-0en_UK
dc.publisher.addressBerlinen_UK
dc.contributor.affiliationComputing Scienceen_UK
dc.contributor.affiliationUniversity of Stirlingen_UK
dc.identifier.wtid831217en_UK
dcterms.dateAccepted2001-12-31en_UK
dc.date.filedepositdate2008-12-18en_UK
rioxxterms.typeConference Paper/Proceeding/Abstracten_UK
rioxxterms.versionAMen_UK
local.rioxx.authorTurner, Kenneth J|en_UK
local.rioxx.authorHe, Ji|en_UK
local.rioxx.projectInternal Project|University of Stirling|https://isni.org/isni/0000000122484331en_UK
local.rioxx.contributorMargaria, Tiziana|en_UK
local.rioxx.contributorMelham, Thomas F|en_UK
local.rioxx.freetoreaddate2008-12-18en_UK
local.rioxx.licencehttp://www.rioxx.net/licenses/all-rights-reserved|2008-12-18|en_UK
local.rioxx.filenameform-des.pdfen_UK
local.rioxx.filecount1en_UK
local.rioxx.source978-3-540-42541-0en_UK
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