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Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/631
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dc.contributor.authorHe, Jien_UK
dc.contributor.authorTurner, Kenneth Jen_UK
dc.contributor.editorBolognesi, Tommasoen_UK
dc.contributor.editorLatella, Diegoen_UK
dc.date.accessioned2017-08-16T22:27:22Z-
dc.date.available2017-08-16T22:27:22Z-
dc.date.issued2000en_UK
dc.identifier.urihttp://hdl.handle.net/1893/631-
dc.description.abstractIt is shown howDILL (Digital Logic in LOTOS) can be used to specify,verify and test asynchronous hardware designs. Asynchronous (unclocked) circuits are a topic of active research in the hardware community. It is illustrated how DILL can address some of the key challenges. New relations for (strong) conformance are defined for assessing a circuit implementation against its specification. An algorithm is also presented for generating and applying implementation tests based on a specification. Tools have been developed for automated verification of conformance and generation of tests. The approach is illustrated with three case studies that explore speed independence, delay sensitivity and testing of sample asynchronous circuit designs.en_UK
dc.language.isoenen_UK
dc.publisherSpringer Verlagen_UK
dc.relationHe J & Turner KJ (2000) Verifying and Testing Asynchronous Circuits using LOTOS (extended version). In: Bolognesi T & Latella D (eds.) Formal Methods for Distributed System Development. IFIP International Federation for Information Processing, vol 55. FORTE/PSTV 2000 - IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XIII) and Protocol Specification, Testing, and Verification (PSTV XX), Pisa, Italy, 10.10.2000-13.10.2000. Amsterdam: Springer Verlag, pp. 267-283. http://www.springer.com/computer/artificial/book/978-0-7923-7968-3?detailsPage=tocen_UK
dc.relation.ispartofseriesIFIP International Federation for Information Processing, vol 55en_UK
dc.rightsPublished by Springer Verlag. The original publication is available at www.springer.comen_UK
dc.titleVerifying and Testing Asynchronous Circuits using LOTOS (extended version)en_UK
dc.typeConference Paperen_UK
dc.citation.spage267en_UK
dc.citation.epage283en_UK
dc.citation.publicationstatusPublisheden_UK
dc.citation.peerreviewedRefereeden_UK
dc.type.statusAM - Accepted Manuscripten_UK
dc.identifier.urlhttp://www.springer.com/computer/artificial/book/978-0-7923-7968-3?detailsPage=tocen_UK
dc.author.emailkjt@cs.stir.ac.uken_UK
dc.citation.btitleFormal Methods for Distributed System Developmenten_UK
dc.citation.conferencedates2000-10-10 - 2000-10-13en_UK
dc.citation.conferencelocationPisa, Italyen_UK
dc.citation.conferencenameFORTE/PSTV 2000 - IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XIII) and Protocol Specification, Testing, and Verification (PSTV XX)en_UK
dc.citation.isbn9780792379683en_UK
dc.publisher.addressAmsterdamen_UK
dc.contributor.affiliationUniversity of Stirlingen_UK
dc.contributor.affiliationComputing Scienceen_UK
dc.identifier.wtid831487en_UK
dcterms.dateAccepted2000-12-31en_UK
dc.date.filedepositdate2008-12-18en_UK
rioxxterms.typeConference Paper/Proceeding/Abstracten_UK
rioxxterms.versionAMen_UK
local.rioxx.authorHe, Ji|en_UK
local.rioxx.authorTurner, Kenneth J|en_UK
local.rioxx.projectInternal Project|University of Stirling|https://isni.org/isni/0000000122484331en_UK
local.rioxx.contributorBolognesi, Tommaso|en_UK
local.rioxx.contributorLatella, Diego|en_UK
local.rioxx.freetoreaddate2008-12-18en_UK
local.rioxx.licencehttp://www.rioxx.net/licenses/all-rights-reserved|2008-12-18|en_UK
local.rioxx.filenameasync-lot.pdfen_UK
local.rioxx.filecount1en_UK
local.rioxx.source9780792379683en_UK
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