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Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/619
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dc.contributor.authorHe, Jien_UK
dc.contributor.authorTurner, Kenneth Jen_UK
dc.contributor.editorMargaria, Tizianaen_UK
dc.contributor.editorMelham, Thomas Fen_UK
dc.date.accessioned2017-07-10T22:57:59Z-
dc.date.available2017-07-10T22:57:59Z-
dc.date.issued2001en_UK
dc.identifier.urihttp://hdl.handle.net/1893/619-
dc.description.abstractIt is explained how DILL (Digital Logic in LOTOS) can be used to specify and analyse hardware timing characteristics using ET-LOTOS (Enhanced Timed LOTOS), a timed extension of the ISO standard formal language LOTOS (Language of Temporal Ordering Specification). Hardware component functionality and timing characteristics are rigorously specified and then validated. As will be seen, subtle timing problems can be found by using this approach.en_UK
dc.language.isoenen_UK
dc.publisherSpringer Verlagen_UK
dc.relationHe J & Turner KJ (2001) Specifying Hardware Timing with ET-LOTOS (extended version). In: Margaria T & Melham TF (eds.) Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science, Volume 2144. CHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Livingston, Scotland, 04.09.2001-07.09.2001. Berlin: Springer Verlag, pp. 161-166. https://doi.org/10.1007/3-540-44798-9_14en_UK
dc.relation.ispartofseriesLecture Notes in Computer Science, Volume 2144en_UK
dc.rightsPublished by Springer Verlag. The original publication is available at www.springerlink.comen_UK
dc.titleSpecifying Hardware Timing with ET-LOTOS (extended version)en_UK
dc.typeConference Paperen_UK
dc.identifier.doi10.1007/3-540-44798-9_14en_UK
dc.citation.spage161en_UK
dc.citation.epage166en_UK
dc.citation.publicationstatusPublisheden_UK
dc.citation.peerreviewedRefereeden_UK
dc.type.statusAM - Accepted Manuscripten_UK
dc.author.emailkjt@cs.stir.ac.uken_UK
dc.citation.btitleCorrect Hardware Design and Verification Methodsen_UK
dc.citation.conferencedates2001-09-04 - 2001-09-07en_UK
dc.citation.conferencelocationLivingston, Scotlanden_UK
dc.citation.conferencenameCHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methodsen_UK
dc.citation.isbn978-3-540-42541-0en_UK
dc.publisher.addressBerlinen_UK
dc.contributor.affiliationUniversity of Stirlingen_UK
dc.contributor.affiliationComputing Scienceen_UK
dc.identifier.wtid830447en_UK
dcterms.dateAccepted2001-12-31en_UK
dc.date.filedepositdate2008-12-16en_UK
rioxxterms.typeConference Paper/Proceeding/Abstracten_UK
rioxxterms.versionAMen_UK
local.rioxx.authorHe, Ji|en_UK
local.rioxx.authorTurner, Kenneth J|en_UK
local.rioxx.projectInternal Project|University of Stirling|https://isni.org/isni/0000000122484331en_UK
local.rioxx.contributorMargaria, Tiziana|en_UK
local.rioxx.contributorMelham, Thomas F|en_UK
local.rioxx.freetoreaddate2008-12-16en_UK
local.rioxx.licencehttp://www.rioxx.net/licenses/all-rights-reserved|2008-12-16|en_UK
local.rioxx.filenamesys-time.pdfen_UK
local.rioxx.filecount1en_UK
local.rioxx.source978-3-540-42541-0en_UK
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