Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/618
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dc.contributor.authorHe, Ji-
dc.contributor.authorTurner, Kenneth J-
dc.contributor.editorWu, Jianping-
dc.contributor.editorChanson, Samuel T-
dc.contributor.editorGao, Quiang-
dc.date.accessioned2017-08-16T23:09:40Z-
dc.date.available2017-08-16T23:09:40Z-
dc.date.issued1999-
dc.identifier.urihttp://hdl.handle.net/1893/618-
dc.description.abstractThis paper investigates specification and verification of synchronous circuits using DILL (Digital Logic in LOTOS). After an overview of the DILL approach, the paper focuses on the characteristics of synchronous circuits. A more constrained model is presented for specifying digital components and verifying them. Two standard benchmark circuits are specified using this new model, and analysed by the CADP toolset (Cæsar/Aldébaran Development Package).en_UK
dc.language.isoen-
dc.publisherSpringer Verlag-
dc.relationHe J & Turner KJ (1999) Specification and Verification of Synchronous Hardware using LOTOS In: Wu Jianping, Chanson Samuel T, Gao Quiang (ed.) Formal Methods for Protocol Engineering and Distributed Systems, Amsterdam: Springer Verlag. FORTE XII /PSTV XIX '99 IFIP TC6/WG 6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols and Protocol Specification, Testing and Verification, 5.10.1999 - 8.10.1999, Beijing, China, pp. 295-312.-
dc.relation.ispartofseriesIFIP International Federation for Information Processing, Vol. 28-
dc.rightsPublished by Springer Verlag. The original publication is available at www.springer.com-
dc.titleSpecification and Verification of Synchronous Hardware using LOTOSen_UK
dc.typeConference Paperen_UK
dc.citation.spage295-
dc.citation.epage312-
dc.citation.publicationstatusPublished-
dc.citation.peerreviewedRefereed-
dc.type.statusPost-print (author final draft post-refereeing)-
dc.identifier.urlhttp://www.springer.com/computer/artificial/book/978-0-7923-8646-9?detailsPage=toc-
dc.author.emailkjt@cs.stir.ac.uk-
dc.citation.btitleFormal Methods for Protocol Engineering and Distributed Systems-
dc.citation.conferencedates1999-10-05T00:00:00Z-
dc.citation.conferencelocationBeijing, China-
dc.citation.conferencenameFORTE XII /PSTV XIX '99 IFIP TC6/WG 6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols and Protocol Specification, Testing and Verification-
dc.citation.isbn9780792386469-
dc.publisher.addressAmsterdam-
dc.contributor.affiliationUniversity of Stirling-
dc.contributor.affiliationComputing Science - CSM Dept-
Appears in Collections:Computing Science and Mathematics Conference Papers and Proceedings

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