Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/28954
Appears in Collections:Computing Science and Mathematics Conference Papers and Proceedings
Author(s): Garcia, Paulo
Bhowmik, Deepayan
Wallace, Andrew
Stewart, Robert
Michaelson, Greg
Title: Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems
Editor(s): Voros, N
Huebner, M
Keramidas, G
Goehringer, D
Antonopoulos, C
Diniz, PC
Citation: Garcia P, Bhowmik D, Wallace A, Stewart R & Michaelson G (2018) Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems. In: Voros N, Huebner M, Keramidas G, Goehringer D, Antonopoulos C & Diniz P (eds.) Applied Reconfigurable Computing. Architectures, Tools, and Applications. Lecture Notes in Computer Science, 10824. ARC 2018: International Symposium on Applied Reconfigurable Computing, Santorini, Greece, 02.05.2018-04.05.2018. Cham, Switzerland: Springer International Publishing, pp. 523-536. https://doi.org/10.1007/978-3-319-78890-6_42
Issue Date: 2018
Series/Report no.: Lecture Notes in Computer Science, 10824
Conference Name: ARC 2018: International Symposium on Applied Reconfigurable Computing
Conference Dates: 2018-05-02 - 2018-05-04
Conference Location: Santorini, Greece
Abstract: This paper presents an orderly dataflow-optimisation approach suitable for area-energy aware computer vision applications on FPGAs. Vision systems are increasingly being deployed in power constrained scenarios, where the dataflow model of computation has become popular for describing complex algorithms. Dataflow model allows processing datapaths comprised of several independent and well defined computations. However, compilers are often unsuccessful in identifying domain-specific optimisation opportunities resulting in wasted resources and power consumption. We present a methodology for the optimisation of dataflow networks, according to patterns often found in computer vision systems, focusing on identifying optimisations which are not discovered automatically by an optimising compiler. Code transformation using profiling and refactoring provides opportunities to optimise the design, targeting FPGA implementations and focusing on area and power abatement. Our refactoring methodology, applying transformations to a complex algorithm for visual tracking resulted in significant reduction in power consumption and resource usage.
Status: AM - Accepted Manuscript
Rights: This is a post-peer-review, pre-copyedit version of a paper published in Voros N, Huebner M, Keramidas G, Goehringer D, Antonopoulos C & Diniz P (eds.) Applied Reconfigurable Computing. Architectures, Tools, and Applications. Lecture Notes in Computer Science, 10824. The final authenticated version is available online at: https://doi.org/10.1007/978-3-319-78890-6_42

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