Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/28508
Appears in Collections:Computing Science and Mathematics Journal Articles
Peer Review Status: Refereed
Title: Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing
Author(s): Garcia, Paulo
Bhowmik, Deepayan
Stewart, Robert
Michaelson, Greg
Wallace, Andrew
Keywords: field programmable gate array (FPGA)
memory
power
image processing
design
Issue Date: 1-Jan-2019
Citation: Garcia P, Bhowmik D, Stewart R, Michaelson G & Wallace A (2019) Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing. Journal of Imaging, 5 (1), Art. No.: 7. https://doi.org/10.3390/jimaging5010007.
Abstract: Memory is the biggest limiting factor to the widespread use of FPGAs for high-level image processing, which require complete frame(s) to be stored in situ. Since FPGAs have limited on-chip memory capabilities, efficient use of such resources is essential to meet performance, size and power constraints. In this paper, we investigate allocation of on-chip memory resources in order to minimize resource usage and power consumption, contributing to the realization of power-efficient high-level image processing fully contained on FPGAs. We propose methods for generating memory architectures, from both Hardware Description Languages and High Level Synthesis designs, which minimize memory usage and power consumption. Based on a formalization of on-chip memory configuration options and a power model, we demonstrate how our partitioning algorithms can outperform traditional strategies. Compared to commercial FPGA synthesis and High Level Synthesis tools, our results show that the proposed algorithms can result in up to 60% higher utilization efficiency, increasing the sizes and/or number of frames that can be accommodated, and reduce frame buffers’ dynamic power consumption by up to approximately 70%. In our experiments using Optical Flow and MeanShift Tracking, representative high-level algorithms, data show that partitioning algorithms can reduce total power by up to 25% and 30%, respectively, without impacting performance.
DOI Link: 10.3390/jimaging5010007
Rights: This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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