Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/27536
Appears in Collections:Computing Science and Mathematics Journal Articles
Peer Review Status: Refereed
Title: Profile Guided Dataflow Transformation for FPGAs and CPUs
Author(s): Stewart, Robert
Bhowmik, Deepayan
Wallace, Andrew
Michaelson, Greg
Contact Email: deepayan.bhowmik@stir.ac.uk
Keywords: dataflow
profiling
transformations
FPGA
CPU
Issue Date: 1-Apr-2017
Citation: Stewart R, Bhowmik D, Wallace A & Michaelson G (2017) Profile Guided Dataflow Transformation for FPGAs and CPUs, Journal of Signal Processing Systems, 87 (1), pp. 3-20. https://doi.org/10.1007/s11265-015-1044-y.
Abstract: This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstractions enables substantial restructuring of FPGA designs before lowering to the HDL level, and also improve CPU performance. Using the CPU transformations, runtime is reduced by 43 %. Using the FPGA transformations, clock frequency is increased from 67MHz to 110MHz. Our results outperform commercial low-level HDL optimisations, showcasing dataflow program abstraction as an amenable computation model for highly effective FPGA optimisation.
DOI Link: 10.1007/s11265-015-1044-y
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