|Appears in Collections:||Computing Science and Mathematics Conference Papers and Proceedings|
|Peer Review Status:||Refereed|
Turner, Kenneth J
|Title:||Specification and Verification of Synchronous Hardware using LOTOS|
Chanson, Samuel T
|Citation:||He J & Turner KJ (1999) Specification and Verification of Synchronous Hardware using LOTOS In: Wu Jianping, Chanson Samuel T, Gao Quiang (ed.) Formal Methods for Protocol Engineering and Distributed Systems, Amsterdam: Springer Verlag. FORTE XII /PSTV XIX '99 IFIP TC6/WG 6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols and Protocol Specification, Testing and Verification, Beijing, China, pp. 295-312.|
|Series/Report no.:||IFIP International Federation for Information Processing, Vol. 28|
|Conference Name:||FORTE XII /PSTV XIX '99 IFIP TC6/WG 6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols and Protocol Specification, Testing and Verification|
|Conference Location:||Beijing, China|
|Abstract:||This paper investigates specification and verification of synchronous circuits using DILL (Digital Logic in LOTOS). After an overview of the DILL approach, the paper focuses on the characteristics of synchronous circuits. A more constrained model is presented for specifying digital components and verifying them. Two standard benchmark circuits are specified using this new model, and analysed by the CADP toolset (Cæsar/Aldébaran Development Package).|
|Status:||Post-print (author final draft post-refereeing)|
|Rights:||Published by Springer Verlag. The original publication is available at www.springer.com|
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