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Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/27565
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dc.contributor.authorBhowmik, Deepayanen_UK
dc.contributor.authorGarcia, Pauloen_UK
dc.contributor.authorWallace, Andrewen_UK
dc.contributor.authorStewart, Roberten_UK
dc.contributor.authorMichaelson, Gregen_UK
dc.date.accessioned2018-07-27T00:00:58Z-
dc.date.available2018-07-27T00:00:58Z-
dc.date.issued2017-09en_UK
dc.identifier.urihttp://hdl.handle.net/1893/27565-
dc.description.abstractThe following topics are dealt with: field programmable gate arrays; cameras; system-on-chip; multiprocessing systems; computer vision; embedded systems; microprocessor chips; object detection; image sensors; mobile robots.en_UK
dc.language.isoenen_UK
dc.publisherIEEEen_UK
dc.relationBhowmik D, Garcia P, Wallace A, Stewart R & Michaelson G (2017) Power efficient dataflow design for a heterogeneous smart camera architecture. In: 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP). 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP), 27.09.2017-29.09.2017. Dresden, Germany: IEEE. https://doi.org/10.1109/dasip.2017.8122128en_UK
dc.rights© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en_UK
dc.subjectField programmable gate arraysen_UK
dc.subjectImage processingen_UK
dc.subjectHardwareen_UK
dc.subjectSmart camerasen_UK
dc.subjectComputer architectureen_UK
dc.subjectComputational modelingen_UK
dc.titlePower efficient dataflow design for a heterogeneous smart camera architectureen_UK
dc.typeConference Paperen_UK
dc.identifier.doi10.1109/dasip.2017.8122128en_UK
dc.citation.publicationstatusPublisheden_UK
dc.type.statusAM - Accepted Manuscripten_UK
dc.contributor.funderEngineering and Physical Sciences Research Councilen_UK
dc.citation.btitle2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)en_UK
dc.citation.conferencedates2017-09-27 - 2017-09-29en_UK
dc.citation.conferencename2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)en_UK
dc.citation.date01/12/2017en_UK
dc.citation.isbn9781538635346en_UK
dc.publisher.addressDresden, Germanyen_UK
dc.contributor.affiliationSheffield Hallam Universityen_UK
dc.contributor.affiliationHeriot-Watt Universityen_UK
dc.contributor.affiliationHeriot-Watt Universityen_UK
dc.contributor.affiliationHeriot-Watt Universityen_UK
dc.contributor.affiliationHeriot-Watt Universityen_UK
dc.identifier.scopusid2-s2.0-85044270501en_UK
dc.identifier.wtid928637en_UK
dc.contributor.orcid0000-0003-1762-1578en_UK
dc.date.accepted2017-07-10en_UK
dcterms.dateAccepted2017-07-10en_UK
dc.date.filedepositdate2018-07-26en_UK
rioxxterms.apcnot requireden_UK
rioxxterms.typeConference Paper/Proceeding/Abstracten_UK
rioxxterms.versionAMen_UK
local.rioxx.authorBhowmik, Deepayan|0000-0003-1762-1578en_UK
local.rioxx.authorGarcia, Paulo|en_UK
local.rioxx.authorWallace, Andrew|en_UK
local.rioxx.authorStewart, Robert|en_UK
local.rioxx.authorMichaelson, Greg|en_UK
local.rioxx.projectProject ID unknown|Engineering and Physical Sciences Research Council|http://dx.doi.org/10.13039/501100000266en_UK
local.rioxx.freetoreaddate2018-07-26en_UK
local.rioxx.licencehttp://www.rioxx.net/licenses/all-rights-reserved|2018-07-26|en_UK
local.rioxx.filenamedasip-2017.pdfen_UK
local.rioxx.filecount1en_UK
local.rioxx.source9781538635346en_UK
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