Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/633
Appears in Collections:Computing Science and Mathematics Conference Papers and Proceedings
Peer Review Status: Refereed
Authors: Turner, Kenneth J
He, Ji
Contact Email: kjt@cs.stir.ac.uk
Title: Formally-Based Design Evaluation (extended version)
Editors: Margaria, Tiziana
Melham, Thomas F
Citation: Turner KJ & He J (2001) Formally-Based Design Evaluation (extended version), Margaria Tiziana, Melham Thomas F (ed.) Correct Hardware Design and Verification Methods, CHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Berlin: Springer Verlag, pp. 104-109.
Issue Date: 2001
Series/Report no.: Lecture Notes in Computer Science,, volume 2144
Conference Name: CHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Abstract: This paper investigates specification, verification and test generation for synchronous and asynchronous circuits. The approach is called DILL (Digital Logic in LOTOS). DILL models are discussed for synchronous and asynchronous circuits. Relations for (strong) conformance are defined for verifying a design specification against a high-level specification. An algorithm is also outlined for generating and applying implementation tests based on a specification. Tools have been developed for automated test generation and verification of conformance between an implementation and its specification. The approach is illustrated with various benchmark circuits as case studies.
Type: Conference Paper
Status: Post-print (author final draft post-refereeing)
Rights: Published by Springer Verlag. The original publication is available at www.springerlink.com
URI: http://hdl.handle.net/1893/633
Affiliation: Computing Science - CSM Dept
University of Stirling

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