|Appears in Collections:||Computing Science and Mathematics Conference Papers and Proceedings|
|Peer Review Status:||Refereed|
Turner, Kenneth J
|Title:||Verifying and Testing Asynchronous Circuits using LOTOS (extended version)|
|Citation:||He J & Turner KJ (2000) Verifying and Testing Asynchronous Circuits using LOTOS (extended version) In: Bolognesi Tommaso, Latella Diego (ed.) Formal Methods for Distributed System Development, Amsterdam: Springer Verlag. FORTE/PSTV 2000 - IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XIII) and Protocol Specification, Testing, and Verification (PSTV XX), 10.10.2000 - 13.10.2000, Pisa, Italy, pp. 267-283.|
|Series/Report no.:||IFIP International Federation for Information Processing, vol 55|
|Conference Name:||FORTE/PSTV 2000 - IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XIII) and Protocol Specification, Testing, and Verification (PSTV XX)|
|Conference Location:||Pisa, Italy|
|Abstract:||It is shown howDILL (Digital Logic in LOTOS) can be used to specify,verify and test asynchronous hardware designs. Asynchronous (unclocked) circuits are a topic of active research in the hardware community. It is illustrated how DILL can address some of the key challenges. New relations for (strong) conformance are defined for assessing a circuit implementation against its specification. An algorithm is also presented for generating and applying implementation tests based on a specification. Tools have been developed for automated verification of conformance and generation of tests. The approach is illustrated with three case studies that explore speed independence, delay sensitivity and testing of sample asynchronous circuit designs.|
|Status:||Post-print (author final draft post-refereeing)|
|Rights:||Published by Springer Verlag. The original publication is available at www.springer.com|
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