|Appears in Collections:||Computing Science and Mathematics Conference Papers and Proceedings|
|Peer Review Status:||Refereed|
Turner, Kenneth J
|Title:||Modelling Digital Logic in SDL|
|Citation:||Csopaki G & Turner KJ (1997) Modelling Digital Logic in SDL In: Mizuno Tadanori, Shiratori Norio, Higashino Teruo, Togashi Atsushi (ed.) Formal Description Techniques and Protocol Specification, Testing and Verification. FORTE X / PSTV XVII '97, Amsterdam: Springer Verlag. FORTE/PSTV'97 - 1997 IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques (X) for Distributed Systems and Communication Protocols, and PROTOCOL SPECIFICATION, TESTING, AND VERIFICATION (XVII), Osaka, Japan, pp. 367-382.|
|Series/Report no.:||IFIP International Federation for Information Processing|
|Conference Name:||FORTE/PSTV'97 - 1997 IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques (X) for Distributed Systems and Communication Protocols, and PROTOCOL SPECIFICATION, TESTING, AND VERIFICATION (XVII)|
|Conference Location:||Osaka, Japan|
|Abstract:||The specification of digital logic in SDL (Specification and Description Language) is investigated. A specification approach is proposed for multi-level descriptions of hardware behaviour and structure. The modelling method exploits features introduced in SDL-92. The approach also deals with the specification, analysis and simulation of timing aspects at any level in the specification of digital logic.|
|Status:||Post-print (author final draft post-refereeing)|
|Rights:||Published by Springer Verlag. The original publication is available at www.springer.com|
This item is protected by original copyright
Items in the Repository are protected by copyright, with all rights reserved, unless otherwise indicated.
If you believe that any material held in STORRE infringes copyright, please contact firstname.lastname@example.org providing details and we will remove the Work from public display in STORRE and investigate your claim.