|Appears in Collections:||Computing Science and Mathematics Conference Papers and Proceedings|
|Peer Review Status:||Refereed|
Turner, Kenneth J
|Title:||Modelling Digital Logic in SDL|
|Citation:||Csopaki G & Turner KJ (1997) Modelling Digital Logic in SDL, Mizuno Tadanori, Shiratori Norio, Higashino Teruo, Togashi Atsushi (ed.) Formal Description Techniques and Protocol Specification, Testing and Verification. FORTE X / PSTV XVII '97, FORTE/PSTV'97 - 1997 IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques (X) for Distributed Systems and Communication Protocols, and PROTOCOL SPECIFICATION, TESTING, AND VERIFICATION (XVII), Osaka, Japan, Amsterdam: Springer Verlag, pp. 367-382.|
|Series/Report no.:||IFIP International Federation for Information Processing|
|Conference Name:||FORTE/PSTV'97 - 1997 IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques (X) for Distributed Systems and Communication Protocols, and PROTOCOL SPECIFICATION, TESTING, AND VERIFICATION (XVII)|
|Conference Location:||Osaka, Japan|
|Abstract:||The specification of digital logic in SDL (Specification and Description Language) is investigated. A specification approach is proposed for multi-level descriptions of hardware behaviour and structure. The modelling method exploits features introduced in SDL-92. The approach also deals with the specification, analysis and simulation of timing aspects at any level in the specification of digital logic.|
|Status:||Post-print (author final draft post-refereeing)|
|Rights:||Published by Springer Verlag. The original publication is available at www.springer.com|
|Affiliation:||Budapest University of Technology And Economics|
Computing Science - CSM Dept
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