|Appears in Collections:||Computing Science and Mathematics Conference Papers and Proceedings|
|Peer Review Status:||Refereed|
Turner, Kenneth J
|Title:||Specifying Hardware Timing with ET-LOTOS (extended version)|
Melham, Thomas F
|Citation:||He J & Turner KJ (2001) Specifying Hardware Timing with ET-LOTOS (extended version), Margaria Tiziana, Melham Thomas F (ed.) Correct Hardware Design and Verification Methods, CHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Berlin: Springer Verlag, pp. 161-166.|
|Series/Report no.:||Lecture Notes in Computer Science, Volume 2144|
|Conference Name:||CHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods|
|Abstract:||It is explained how DILL (Digital Logic in LOTOS) can be used to specify and analyse hardware timing characteristics using ET-LOTOS (Enhanced Timed LOTOS), a timed extension of the ISO standard formal language LOTOS (Language of Temporal Ordering Specification). Hardware component functionality and timing characteristics are rigorously specified and then validated. As will be seen, subtle timing problems can be found by using this approach.|
|Status:||Post-print (author final draft post-refereeing)|
|Rights:||Published by Springer Verlag. The original publication is available at www.springerlink.com|
|Affiliation:||University of Stirling|
Computing Science - CSM Dept
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