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http://hdl.handle.net/1893/619| Appears in Collections: | Computing Science and Mathematics Conference Papers and Proceedings |
| Peer Review Status: | Refereed |
| Author(s): | He, Ji Turner, Kenneth J |
| Contact Email: | kjt@cs.stir.ac.uk |
| Title: | Specifying Hardware Timing with ET-LOTOS (extended version) |
| Editor(s): | Margaria, Tiziana Melham, Thomas F |
| Citation: | He J & Turner KJ (2001) Specifying Hardware Timing with ET-LOTOS (extended version). In: Margaria T & Melham TF (eds.) Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science, Volume 2144. CHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Livingston, Scotland, 04.09.2001-07.09.2001. Berlin: Springer Verlag, pp. 161-166. https://doi.org/10.1007/3-540-44798-9_14 |
| Issue Date: | 2001 |
| Date Deposited: | 16-Dec-2008 |
| Series/Report no.: | Lecture Notes in Computer Science, Volume 2144 |
| Conference Name: | CHARME 2001 - 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods |
| Conference Dates: | 2001-09-04 - 2001-09-07 |
| Conference Location: | Livingston, Scotland |
| Abstract: | It is explained how DILL (Digital Logic in LOTOS) can be used to specify and analyse hardware timing characteristics using ET-LOTOS (Enhanced Timed LOTOS), a timed extension of the ISO standard formal language LOTOS (Language of Temporal Ordering Specification). Hardware component functionality and timing characteristics are rigorously specified and then validated. As will be seen, subtle timing problems can be found by using this approach. |
| Status: | AM - Accepted Manuscript |
| Rights: | Published by Springer Verlag. The original publication is available at www.springerlink.com |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| sys-time.pdf | Fulltext - Accepted Version | 121.91 kB | Adobe PDF | View/Open |
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