Please use this identifier to cite or link to this item: http://hdl.handle.net/1893/616
Appears in Collections:Computing Science and Mathematics Conference Papers and Proceedings
Peer Review Status: Refereed
Authors: Turner, Kenneth J
Argul-Marin, F Javier
Laing, Stephen D
Contact Email: kjt@cs.stir.ac.uk
Title: Concurrent Specification and Timing Analysis of Digital Hardware using SDL (extended version)
Editors: Rolim, Jose
Citation: Turner KJ, Argul-Marin FJ & Laing SD (2000) Concurrent Specification and Timing Analysis of Digital Hardware using SDL (extended version) In: Rolim Jose (ed.) Parallel and Distributed Processing, Berlin: Springer Verlag. IPDPS 2000 - International Parallel & Distributed Processing Symposium, pp. 1001-1008.
Issue Date: 2000
Series/Report no.: Lecture Notes in Computer Science, Volume 1800
Conference Name: IPDPS 2000 - International Parallel & Distributed Processing Symposium
Abstract: Digital hardware is treated as a collection of interacting parallel components. This permits the use of a standard formal technique for specification and analysis of circuit designs. The ANISEED method (Analysis In SDL Enhancing Electronic Design) is presented for specifying and analysing timing characteristics of hardware designs using SDL (Specification and Description Language). A signal carries a binary value and an optional time-stamp. Components and circuit designs are instances of block types in library packages. The library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abstract, behavioural or structural level. Timing properties are investigated using an SDL simulator or validator. Consistency of temporal and functional aspects may be assessed between designs at different levels of detail. Timing characteristics of a design may also be inferred from validator traces. A variety of examples is used, ranging from a simple gate specification to realistic examples drawn from a standard hardware verification benchmark.
Type: Conference Paper
Status: Post-print (author final draft post-refereeing)
Rights: Published by Springer Verlag. The original publication is available at www.springerlink.com
URI: http://hdl.handle.net/1893/616
Affiliation: Computing Science - CSM Dept
University of Stirling
University of Stirling

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